This invention relates to programmable logic integrated circuit devices, and more particularly to the organization of particular types of interconnection conductors on such devices.
Programmable logic devices with areas of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such areas are well known as shown, for example, by Cliff et al. U.S. Pat. No. 5,689,195, which is hereby incorporated by reference herein in its entirety. Advances in integrated circuit fabrication technology are making it possible to make such programmable logic devices both larger and denser. For example, more and more areas of programmable logic can be put on such devices by making the device larger, or denser, or both larger and denser.
Many desired uses of programmable logic devices require certain signals to be supplied to many logic areas. For example, many logic areas may need to receive the same register clocking or register clearing (xe2x80x9ccontrolxe2x80x9d) signals. Or many areas may need to receive the same xe2x80x9cdataxe2x80x9d signal. In some cases each of several data or control signals may need to go to respective different groups of logic areas, each such group including many areas. Some of the data or control signals requiring dispersion to many logic areas may need to come from outside the device, while others may need to be generated on the device.
Efficient networks are needed for allowing flexible distribution of very wide fan-out signals of the type described above. Because such a network must extend so extensively throughout the device, the number of conductors in the network should be kept relatively low to avoid devoting an undue proportion of the total resources of the device to these conductors and the connections from these conductors to each logic area on the device. The network should also preferably be designed for rapid dissemination of the signals on the network because these widely used signals should not hold back the operating speed of the device. In fact, a network of this type may be called a xe2x80x9cfast conductorxe2x80x9d or xe2x80x9cfast signalxe2x80x9d network to indicate the desirability of rapid propagation of signals on the network. The network should allow signals to reach any logic area on the device with relatively little delay, and there should also be relatively little xe2x80x9cskewxe2x80x9d associated with the network. (Skew refers to different amounts of delay being associated with reaching different logic areas on the device.)
In view of the foregoing, it is an object of this invention to provide improved fast conductor networks for programmable logic devices.
It is a more particular object of this invention to provide fast conductor networks which require relatively small amounts of the overall resources of the device, but which are capable of rapidly and flexibly distributing either external or internal signals throughout the device with relatively little skew.
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing a fast conductor network for a programmable logic device that has a plurality of areas of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such areas. The fast conductor network preferably includes several main conductors that extend across the device so as to bisect the device (e.g., by extending parallel to the columns of logic areas at a location which bisects each row of the logic areas). Some of these main conductors receive signals from input pins of the device. These input pin connections are preferably relatively direct and xe2x80x9cdedicatedxe2x80x9d to help reduce delay. (A dedicated connection is one which goes only to a conductor in the fast conductor network and which therefore does not require switching or have other uses that can increase the associated signal loading and delay.) Others of these main conductors receive signals from logic areas on the device. The logic areas that can supply signals to the main conductors are preferably adjacent to the main conductors to help reduce delay associated with disseminating those signals. Drivers may be provided in the main conductors to help strengthen and speed the signals on these conductors.
Assuming that the main fast conductors extend parallel to the columns of logic areas, then several secondary fast conductors are associated with each row of the logic areas. The secondary fast conductors associated with each row extend along that row. Programmable logic connectors (xe2x80x9cPLCsxe2x80x9d) are associated with each row""s group of secondary fast conductors for selectively applying signals from the main conductors to the secondary conductors. Additional PLCs are associated with each logic area for selectively applying signals from that row""s group of secondary fast conductors to that area""s logic. These connections are preferably such that the fast signals can be used by the receiving area either as data or as control signals. For example, a data signal can be one of the xe2x80x9clogicxe2x80x9d inputs applied to a look-up table in the logic area to cause the look-up table to select and output a logic output signal. Alternatively, a control signal to a logic area can control a function of a register in the area. Examples of register functions that may be thus controlled are clocking or clearing the register.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.